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[/] [pci/] [tags/] [rel_1/] - Rev 26

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Rev Log message Author Age Path
26 Modified testbench and fixed some bugs mihad 8163d 23h /pci/tags/rel_1/
25 *** empty log message *** mihad 8181d 22h /pci/tags/rel_1/
24 *** empty log message *** mihad 8181d 22h /pci/tags/rel_1/
23 *** empty log message *** mihad 8182d 00h /pci/tags/rel_1/
22 Added short description for simulation running mihad 8182d 00h /pci/tags/rel_1/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8182d 01h /pci/tags/rel_1/
20 *** empty log message *** mihad 8182d 01h /pci/tags/rel_1/
19 *** empty log message *** mihad 8182d 01h /pci/tags/rel_1/
18 *** empty log message *** mihad 8182d 01h /pci/tags/rel_1/
17 *** empty log message *** mihad 8182d 02h /pci/tags/rel_1/
16 Import of various scripts for simulation running mihad 8182d 02h /pci/tags/rel_1/
15 Initial testbench import. Still under development mihad 8182d 02h /pci/tags/rel_1/
14 *** empty log message *** mihad 8182d 02h /pci/tags/rel_1/
13 Added separate software directory to the project mihad 8182d 03h /pci/tags/rel_1/
12 PCI IP Core Introduction mihad 8183d 22h /pci/tags/rel_1/
11 Initial design document release mihad 8183d 22h /pci/tags/rel_1/
10 Updated descriptions, functional changes, added software obligations chapter mihad 8183d 23h /pci/tags/rel_1/
9 Update the Configuration Space and REGISTERS description mihad 8284d 07h /pci/tags/rel_1/
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8301d 08h /pci/tags/rel_1/
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8301d 08h /pci/tags/rel_1/

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