URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 51

Rev	Log message	Author	Age	Path
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7978d 19h	/pci/tags/rel_1/bench/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7987d 17h	/pci/tags/rel_1/bench/verilog/
44	Added for testing of Configuration Cycles Type 1	mihad	7987d 18h	/pci/tags/rel_1/bench/verilog/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7987d 18h	/pci/tags/rel_1/bench/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8132d 21h	/pci/tags/rel_1/bench/verilog/
34	Added missing include statements	mihad	8147d 19h	/pci/tags/rel_1/bench/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8148d 17h	/pci/tags/rel_1/bench/verilog/
26	Modified testbench and fixed some bugs	mihad	8162d 12h	/pci/tags/rel_1/bench/verilog/
19	* empty log message *	mihad	8180d 13h	/pci/tags/rel_1/bench/verilog/
15	Initial testbench import. Still under development	mihad	8180d 15h	/pci/tags/rel_1/bench/verilog/
3	New project directory structure	mihad	8302d 12h	/pci/tags/rel_1/bench/verilog/