OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5576d 20h /pci/tags/rel_1/rtl/verilog/
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7929d 11h /pci/tags/rel_1/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7929d 11h /pci/tags/rel_1/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7929d 12h /pci/tags/rel_1/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7934d 12h /pci/tags/rel_1/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7934d 18h /pci/tags/rel_1/rtl/verilog/
56 Number of state bits define was removed mihad 7935d 09h /pci/tags/rel_1/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7935d 10h /pci/tags/rel_1/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7968d 15h /pci/tags/rel_1/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7968d 19h /pci/tags/rel_1/rtl/verilog/
50 Got rid of undef directives mihad 7971d 11h /pci/tags/rel_1/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7971d 11h /pci/tags/rel_1/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7971d 11h /pci/tags/rel_1/rtl/verilog/
47 Known issues repaired mihad 7971d 17h /pci/tags/rel_1/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7976d 11h /pci/tags/rel_1/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7977d 17h /pci/tags/rel_1/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8122d 20h /pci/tags/rel_1/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8138d 16h /pci/tags/rel_1/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8146d 13h /pci/tags/rel_1/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8152d 11h /pci/tags/rel_1/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.