URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 32

Rev	Log message	Author	Age	Path
32	Added include statement that was missing and causing errors	mihad	8192d 01h	/pci/tags/rel_1/rtl/verilog/
26	Modified testbench and fixed some bugs	mihad	8198d 00h	/pci/tags/rel_1/rtl/verilog/
23	* empty log message *	mihad	8216d 00h	/pci/tags/rel_1/rtl/verilog/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8216d 01h	/pci/tags/rel_1/rtl/verilog/
19	* empty log message *	mihad	8216d 01h	/pci/tags/rel_1/rtl/verilog/
18	* empty log message *	mihad	8216d 01h	/pci/tags/rel_1/rtl/verilog/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8335d 08h	/pci/tags/rel_1/rtl/verilog/
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8335d 08h	/pci/tags/rel_1/rtl/verilog/
2	New project directory structure	mihad	8338d 01h	/pci/tags/rel_1/rtl/verilog/