OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] - Rev 54

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7976d 09h /pci/tags/rel_10/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7976d 13h /pci/tags/rel_10/
52 Oops, never before noticed that OC header is missing mihad 7976d 17h /pci/tags/rel_10/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7976d 17h /pci/tags/rel_10/
50 Got rid of undef directives mihad 7979d 09h /pci/tags/rel_10/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7979d 09h /pci/tags/rel_10/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7979d 09h /pci/tags/rel_10/
47 Known issues repaired mihad 7979d 15h /pci/tags/rel_10/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7984d 10h /pci/tags/rel_10/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7985d 15h /pci/tags/rel_10/
44 Added for testing of Configuration Cycles Type 1 mihad 7985d 16h /pci/tags/rel_10/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7985d 16h /pci/tags/rel_10/
42 Removed out of date files mihad 7997d 16h /pci/tags/rel_10/
40 From these Wrod files PDF were created - added future improvements tadej 8076d 07h /pci/tags/rel_10/
39 File not needed tadej 8076d 08h /pci/tags/rel_10/
38 This file is not needed tadej 8076d 10h /pci/tags/rel_10/
37 These files are not needed any more tadej 8076d 11h /pci/tags/rel_10/
36 *** empty log message *** tadej 8076d 11h /pci/tags/rel_10/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8130d 19h /pci/tags/rel_10/
34 Added missing include statements mihad 8145d 17h /pci/tags/rel_10/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.