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[/] [pci/] [tags/] [rel_10/] - Rev 88

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Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7761d 09h /pci/tags/rel_10/
87 Updated acording to RTL changes. mihad 7773d 06h /pci/tags/rel_10/
86 Entered the option to disable no response counter in wb master. mihad 7773d 06h /pci/tags/rel_10/
85 Changed Vendor ID defines. mihad 7773d 11h /pci/tags/rel_10/
84 Changed vendor ID. mihad 7777d 05h /pci/tags/rel_10/
83 Cleaned up the code. No functional changes. mihad 7802d 03h /pci/tags/rel_10/
81 Updated synchronization in top level fifo modules. mihad 7816d 00h /pci/tags/rel_10/
79 Updated. mihad 7819d 05h /pci/tags/rel_10/
78 Old files with wrong names removed. mihad 7819d 05h /pci/tags/rel_10/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7819d 05h /pci/tags/rel_10/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7822d 05h /pci/tags/rel_10/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7825d 05h /pci/tags/rel_10/
73 Bug fixes, testcases added. mihad 7825d 06h /pci/tags/rel_10/
72 *** empty log message *** mihad 7872d 10h /pci/tags/rel_10/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7880d 01h /pci/tags/rel_10/
69 Changed BIST signal names etc.. mihad 7917d 09h /pci/tags/rel_10/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7920d 18h /pci/tags/rel_10/
67 Changed BIST signals for RAMs. tadejm 7920d 23h /pci/tags/rel_10/
66 Changed empty status generation in pciw_fifo_control.v mihad 7924d 09h /pci/tags/rel_10/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7927d 08h /pci/tags/rel_10/

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