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[/] [pci/] [tags/] [rel_10/] [apps/] [crt/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5567d 14h /pci/tags/rel_10/apps/crt/
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7531d 13h /pci/tags/rel_10/apps/crt/
96 Update! mihad 7665d 12h /pci/tags/rel_10/apps/crt/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7701d 10h /pci/tags/rel_10/apps/crt/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7701d 10h /pci/tags/rel_10/apps/crt/
84 Changed vendor ID. mihad 7759d 06h /pci/tags/rel_10/apps/crt/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7801d 06h /pci/tags/rel_10/apps/crt/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7804d 05h /pci/tags/rel_10/apps/crt/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7807d 06h /pci/tags/rel_10/apps/crt/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7920d 07h /pci/tags/rel_10/apps/crt/
31 User defined constants used for Test Application tadej 8140d 02h /pci/tags/rel_10/apps/crt/
29 Xilinx synthesys log file tadej 8140d 13h /pci/tags/rel_10/apps/crt/
25 *** empty log message *** mihad 8161d 05h /pci/tags/rel_10/apps/crt/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8161d 07h /pci/tags/rel_10/apps/crt/
14 *** empty log message *** mihad 8161d 09h /pci/tags/rel_10/apps/crt/
2 New project directory structure mihad 8283d 07h /pci/tags/rel_10/apps/crt/

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