URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [apps/] [crt/] [syn/] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5578d 11h	/pci/tags/rel_10/apps/crt/syn/
125	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7542d 09h	/pci/tags/rel_10/apps/crt/syn/
96	Update!	mihad	7676d 09h	/pci/tags/rel_10/apps/crt/syn/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7712d 06h	/pci/tags/rel_10/apps/crt/syn/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7712d 06h	/pci/tags/rel_10/apps/crt/syn/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7812d 02h	/pci/tags/rel_10/apps/crt/syn/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7815d 02h	/pci/tags/rel_10/apps/crt/syn/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7931d 03h	/pci/tags/rel_10/apps/crt/syn/
29	Xilinx synthesys log file	tadej	8151d 10h	/pci/tags/rel_10/apps/crt/syn/
25	* empty log message *	mihad	8172d 01h	/pci/tags/rel_10/apps/crt/syn/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8172d 04h	/pci/tags/rel_10/apps/crt/syn/
2	New project directory structure	mihad	8294d 03h	/pci/tags/rel_10/apps/crt/syn/