URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_10/] [bench/] [verilog/] - Rev 107

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Rev	Log message	Author	Age	Path
107	Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry.	tadejm	7631d 09h	/pci/tags/rel_10/bench/verilog/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7636d 08h	/pci/tags/rel_10/bench/verilog/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7641d 17h	/pci/tags/rel_10/bench/verilog/
92	Update!	mihad	7688d 23h	/pci/tags/rel_10/bench/verilog/
89	Burst 2 error fixed.	mihad	7760d 13h	/pci/tags/rel_10/bench/verilog/
87	Updated acording to RTL changes.	mihad	7778d 10h	/pci/tags/rel_10/bench/verilog/
81	Updated synchronization in top level fifo modules.	mihad	7821d 04h	/pci/tags/rel_10/bench/verilog/
73	Bug fixes, testcases added.	mihad	7830d 10h	/pci/tags/rel_10/bench/verilog/
69	Changed BIST signal names etc..	mihad	7922d 13h	/pci/tags/rel_10/bench/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7929d 13h	/pci/tags/rel_10/bench/verilog/
64	The testcase I just added in previous revision repaired	mihad	7932d 14h	/pci/tags/rel_10/bench/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7932d 16h	/pci/tags/rel_10/bench/verilog/
62	Added BIST signals for RAMs.	mihad	7935d 08h	/pci/tags/rel_10/bench/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7948d 16h	/pci/tags/rel_10/bench/verilog/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7982d 09h	/pci/tags/rel_10/bench/verilog/
52	Oops, never before noticed that OC header is missing	mihad	7982d 16h	/pci/tags/rel_10/bench/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7982d 17h	/pci/tags/rel_10/bench/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7991d 15h	/pci/tags/rel_10/bench/verilog/
44	Added for testing of Configuration Cycles Type 1	mihad	7991d 15h	/pci/tags/rel_10/bench/verilog/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7991d 15h	/pci/tags/rel_10/bench/verilog/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [bench/] [verilog/] - Rev 107

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