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[/] [pci/] [tags/] [rel_10/] [bench/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5582d 19h /pci/tags/rel_10/bench/verilog/
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7546d 18h /pci/tags/rel_10/bench/verilog/
122 mbist signals updated according to newest convention markom 7553d 18h /pci/tags/rel_10/bench/verilog/
119 Added support for WB B3. Some testcases were updated. tadejm 7610d 06h /pci/tags/rel_10/bench/verilog/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7623d 11h /pci/tags/rel_10/bench/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7628d 09h /pci/tags/rel_10/bench/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7633d 19h /pci/tags/rel_10/bench/verilog/
92 Update! mihad 7681d 01h /pci/tags/rel_10/bench/verilog/
89 Burst 2 error fixed. mihad 7752d 15h /pci/tags/rel_10/bench/verilog/
87 Updated acording to RTL changes. mihad 7770d 12h /pci/tags/rel_10/bench/verilog/
81 Updated synchronization in top level fifo modules. mihad 7813d 05h /pci/tags/rel_10/bench/verilog/
73 Bug fixes, testcases added. mihad 7822d 11h /pci/tags/rel_10/bench/verilog/
69 Changed BIST signal names etc.. mihad 7914d 14h /pci/tags/rel_10/bench/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7921d 15h /pci/tags/rel_10/bench/verilog/
64 The testcase I just added in previous revision repaired mihad 7924d 15h /pci/tags/rel_10/bench/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7924d 17h /pci/tags/rel_10/bench/verilog/
62 Added BIST signals for RAMs. mihad 7927d 10h /pci/tags/rel_10/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7940d 17h /pci/tags/rel_10/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7974d 10h /pci/tags/rel_10/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7974d 18h /pci/tags/rel_10/bench/verilog/

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