URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [rtl/] - Rev 57

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7987d 09h	/pci/tags/rel_10/rtl/
56	Number of state bits define was removed	mihad	7988d 00h	/pci/tags/rel_10/rtl/
55	Changed state machine encoding to true one-hot	mihad	7988d 00h	/pci/tags/rel_10/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8021d 05h	/pci/tags/rel_10/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8021d 10h	/pci/tags/rel_10/rtl/
50	Got rid of undef directives	mihad	8024d 02h	/pci/tags/rel_10/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8024d 02h	/pci/tags/rel_10/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8024d 02h	/pci/tags/rel_10/rtl/
47	Known issues repaired	mihad	8024d 08h	/pci/tags/rel_10/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8029d 02h	/pci/tags/rel_10/rtl/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8030d 08h	/pci/tags/rel_10/rtl/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8175d 11h	/pci/tags/rel_10/rtl/
33	Added some testcases, removed un-needed fifo signals	mihad	8191d 07h	/pci/tags/rel_10/rtl/
32	Added include statement that was missing and causing errors	mihad	8199d 04h	/pci/tags/rel_10/rtl/
26	Modified testbench and fixed some bugs	mihad	8205d 02h	/pci/tags/rel_10/rtl/
23	* empty log message *	mihad	8223d 03h	/pci/tags/rel_10/rtl/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8223d 04h	/pci/tags/rel_10/rtl/
19	* empty log message *	mihad	8223d 04h	/pci/tags/rel_10/rtl/
18	* empty log message *	mihad	8223d 04h	/pci/tags/rel_10/rtl/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8342d 11h	/pci/tags/rel_10/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [rtl/] - Rev 57

Filtering Options