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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] - Rev 116

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Rev	Log message	Author	Age	Path
116	Corrected bug when writing to FIFO (now it is registered).	tadejm	7653d 00h	/pci/tags/rel_10/rtl/verilog/
115	Added signals for WB Master B3.	tadejm	7653d 00h	/pci/tags/rel_10/rtl/verilog/
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7660d 03h	/pci/tags/rel_10/rtl/verilog/
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7660d 08h	/pci/tags/rel_10/rtl/verilog/
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7662d 07h	/pci/tags/rel_10/rtl/verilog/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7666d 04h	/pci/tags/rel_10/rtl/verilog/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7671d 03h	/pci/tags/rel_10/rtl/verilog/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7676d 12h	/pci/tags/rel_10/rtl/verilog/
94	Changed one critical PCI bus signal logic.	mihad	7723d 10h	/pci/tags/rel_10/rtl/verilog/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7801d 07h	/pci/tags/rel_10/rtl/verilog/
86	Entered the option to disable no response counter in wb master.	mihad	7813d 05h	/pci/tags/rel_10/rtl/verilog/
83	Cleaned up the code. No functional changes.	mihad	7842d 02h	/pci/tags/rel_10/rtl/verilog/
81	Updated synchronization in top level fifo modules.	mihad	7855d 23h	/pci/tags/rel_10/rtl/verilog/
79	Updated.	mihad	7859d 04h	/pci/tags/rel_10/rtl/verilog/
78	Old files with wrong names removed.	mihad	7859d 04h	/pci/tags/rel_10/rtl/verilog/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7859d 04h	/pci/tags/rel_10/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7865d 05h	/pci/tags/rel_10/rtl/verilog/
72	* empty log message *	mihad	7912d 08h	/pci/tags/rel_10/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7920d 00h	/pci/tags/rel_10/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7957d 08h	/pci/tags/rel_10/rtl/verilog/

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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] - Rev 116

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