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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] - Rev 60

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Rev	Log message	Author	Age	Path
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7955d 01h	/pci/tags/rel_10/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7955d 02h	/pci/tags/rel_10/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7960d 02h	/pci/tags/rel_10/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7960d 08h	/pci/tags/rel_10/rtl/verilog/
56	Number of state bits define was removed	mihad	7960d 23h	/pci/tags/rel_10/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7961d 00h	/pci/tags/rel_10/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7994d 05h	/pci/tags/rel_10/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7994d 09h	/pci/tags/rel_10/rtl/verilog/
50	Got rid of undef directives	mihad	7997d 01h	/pci/tags/rel_10/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7997d 02h	/pci/tags/rel_10/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7997d 02h	/pci/tags/rel_10/rtl/verilog/
47	Known issues repaired	mihad	7997d 07h	/pci/tags/rel_10/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8002d 02h	/pci/tags/rel_10/rtl/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8003d 07h	/pci/tags/rel_10/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8148d 11h	/pci/tags/rel_10/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8164d 06h	/pci/tags/rel_10/rtl/verilog/
32	Added include statement that was missing and causing errors	mihad	8172d 03h	/pci/tags/rel_10/rtl/verilog/
26	Modified testbench and fixed some bugs	mihad	8178d 02h	/pci/tags/rel_10/rtl/verilog/
23	* empty log message *	mihad	8196d 02h	/pci/tags/rel_10/rtl/verilog/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8196d 03h	/pci/tags/rel_10/rtl/verilog/

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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] - Rev 60

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