OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [sim/] [rtl_sim/] - Rev 77

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7862d 04h /pci/tags/rel_10/sim/rtl_sim/
73 Bug fixes, testcases added. mihad 7868d 05h /pci/tags/rel_10/sim/rtl_sim/
72 *** empty log message *** mihad 7915d 09h /pci/tags/rel_10/sim/rtl_sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7970d 11h /pci/tags/rel_10/sim/rtl_sim/
62 Added BIST signals for RAMs. mihad 7973d 04h /pci/tags/rel_10/sim/rtl_sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7981d 04h /pci/tags/rel_10/sim/rtl_sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7981d 05h /pci/tags/rel_10/sim/rtl_sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8020d 12h /pci/tags/rel_10/sim/rtl_sim/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8023d 04h /pci/tags/rel_10/sim/rtl_sim/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8029d 10h /pci/tags/rel_10/sim/rtl_sim/
42 Removed out of date files mihad 8041d 11h /pci/tags/rel_10/sim/rtl_sim/
30 Example of PCI testbench log file mihad 8201d 09h /pci/tags/rel_10/sim/rtl_sim/
27 Modified testbench and fixed some bugs mihad 8204d 04h /pci/tags/rel_10/sim/rtl_sim/
26 Modified testbench and fixed some bugs mihad 8204d 05h /pci/tags/rel_10/sim/rtl_sim/
22 Added short description for simulation running mihad 8222d 05h /pci/tags/rel_10/sim/rtl_sim/
17 *** empty log message *** mihad 8222d 07h /pci/tags/rel_10/sim/rtl_sim/
16 Import of various scripts for simulation running mihad 8222d 07h /pci/tags/rel_10/sim/rtl_sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.