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[/] [pci/] [tags/] [rel_11/] [apps/] - Rev 102

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Rev Log message Author Age Path
102 Cleanup! mihad 7680d 14h /pci/tags/rel_11/apps/
101 Added simulation files. mihad 7680d 14h /pci/tags/rel_11/apps/
100 Cleanup! mihad 7680d 14h /pci/tags/rel_11/apps/
99 Cleanup! mihad 7680d 14h /pci/tags/rel_11/apps/
98 Cleanup. mihad 7680d 14h /pci/tags/rel_11/apps/
97 Doing a little bit of cleanup. mihad 7680d 14h /pci/tags/rel_11/apps/
96 Update! mihad 7680d 15h /pci/tags/rel_11/apps/
93 Added a test application! mihad 7680d 22h /pci/tags/rel_11/apps/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7716d 12h /pci/tags/rel_11/apps/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7716d 12h /pci/tags/rel_11/apps/
85 Changed Vendor ID defines. mihad 7770d 14h /pci/tags/rel_11/apps/
84 Changed vendor ID. mihad 7774d 08h /pci/tags/rel_11/apps/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7816d 08h /pci/tags/rel_11/apps/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7819d 08h /pci/tags/rel_11/apps/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7822d 09h /pci/tags/rel_11/apps/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7935d 09h /pci/tags/rel_11/apps/
38 This file is not needed tadej 8074d 09h /pci/tags/rel_11/apps/
36 *** empty log message *** tadej 8074d 10h /pci/tags/rel_11/apps/
31 User defined constants used for Test Application tadej 8155d 05h /pci/tags/rel_11/apps/
29 Xilinx synthesys log file tadej 8155d 16h /pci/tags/rel_11/apps/

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