OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [rtl/] - Rev 88

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7831d 06h /pci/tags/rel_11/rtl/
86 Entered the option to disable no response counter in wb master. mihad 7843d 04h /pci/tags/rel_11/rtl/
83 Cleaned up the code. No functional changes. mihad 7872d 01h /pci/tags/rel_11/rtl/
81 Updated synchronization in top level fifo modules. mihad 7885d 21h /pci/tags/rel_11/rtl/
79 Updated. mihad 7889d 02h /pci/tags/rel_11/rtl/
78 Old files with wrong names removed. mihad 7889d 02h /pci/tags/rel_11/rtl/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7889d 02h /pci/tags/rel_11/rtl/
73 Bug fixes, testcases added. mihad 7895d 03h /pci/tags/rel_11/rtl/
72 *** empty log message *** mihad 7942d 07h /pci/tags/rel_11/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7949d 23h /pci/tags/rel_11/rtl/
69 Changed BIST signal names etc.. mihad 7987d 06h /pci/tags/rel_11/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7990d 16h /pci/tags/rel_11/rtl/
67 Changed BIST signals for RAMs. tadejm 7990d 20h /pci/tags/rel_11/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7994d 07h /pci/tags/rel_11/rtl/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7997d 05h /pci/tags/rel_11/rtl/
63 Added additional testcase and changed rst name in BIST to trst mihad 7997d 09h /pci/tags/rel_11/rtl/
62 Added BIST signals for RAMs. mihad 8000d 02h /pci/tags/rel_11/rtl/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8008d 02h /pci/tags/rel_11/rtl/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8008d 03h /pci/tags/rel_11/rtl/
58 Removed all logic from asynchronous reset network mihad 8013d 03h /pci/tags/rel_11/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.