OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5565d 14h /pci/tags/rel_11/rtl/verilog/
127 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7491d 06h /pci/tags/rel_11/rtl/verilog/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7491d 06h /pci/tags/rel_11/rtl/verilog/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7529d 13h /pci/tags/rel_11/rtl/verilog/
122 mbist signals updated according to newest convention markom 7536d 13h /pci/tags/rel_11/rtl/verilog/
117 WB Master is now WISHBONE B3 compatible. tadejm 7593d 01h /pci/tags/rel_11/rtl/verilog/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7593d 01h /pci/tags/rel_11/rtl/verilog/
115 Added signals for WB Master B3. tadejm 7593d 01h /pci/tags/rel_11/rtl/verilog/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7600d 04h /pci/tags/rel_11/rtl/verilog/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7600d 09h /pci/tags/rel_11/rtl/verilog/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7602d 08h /pci/tags/rel_11/rtl/verilog/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7606d 06h /pci/tags/rel_11/rtl/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7611d 04h /pci/tags/rel_11/rtl/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7616d 14h /pci/tags/rel_11/rtl/verilog/
94 Changed one critical PCI bus signal logic. mihad 7663d 12h /pci/tags/rel_11/rtl/verilog/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7741d 09h /pci/tags/rel_11/rtl/verilog/
86 Entered the option to disable no response counter in wb master. mihad 7753d 07h /pci/tags/rel_11/rtl/verilog/
83 Cleaned up the code. No functional changes. mihad 7782d 04h /pci/tags/rel_11/rtl/verilog/
81 Updated synchronization in top level fifo modules. mihad 7796d 00h /pci/tags/rel_11/rtl/verilog/
79 Updated. mihad 7799d 05h /pci/tags/rel_11/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.