OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [sim/] - Rev 63

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7919d 16h /pci/tags/rel_11/sim/
62 Added BIST signals for RAMs. mihad 7922d 09h /pci/tags/rel_11/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7930d 09h /pci/tags/rel_11/sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7930d 10h /pci/tags/rel_11/sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7969d 17h /pci/tags/rel_11/sim/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7972d 10h /pci/tags/rel_11/sim/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7978d 15h /pci/tags/rel_11/sim/
42 Removed out of date files mihad 7990d 16h /pci/tags/rel_11/sim/
30 Example of PCI testbench log file mihad 8150d 14h /pci/tags/rel_11/sim/
27 Modified testbench and fixed some bugs mihad 8153d 09h /pci/tags/rel_11/sim/
26 Modified testbench and fixed some bugs mihad 8153d 10h /pci/tags/rel_11/sim/
22 Added short description for simulation running mihad 8171d 11h /pci/tags/rel_11/sim/
20 *** empty log message *** mihad 8171d 11h /pci/tags/rel_11/sim/
17 *** empty log message *** mihad 8171d 13h /pci/tags/rel_11/sim/
16 Import of various scripts for simulation running mihad 8171d 13h /pci/tags/rel_11/sim/
3 New project directory structure mihad 8293d 11h /pci/tags/rel_11/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.