URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] - Rev 103

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Rev	Log message	Author	Age	Path
103	Added test application and modified files to support it.	mihad	7746d 23h	/pci/tags/rel_12/
102	Cleanup!	mihad	7746d 23h	/pci/tags/rel_12/
101	Added simulation files.	mihad	7746d 23h	/pci/tags/rel_12/
100	Cleanup!	mihad	7746d 23h	/pci/tags/rel_12/
99	Cleanup!	mihad	7746d 23h	/pci/tags/rel_12/
98	Cleanup.	mihad	7746d 23h	/pci/tags/rel_12/
97	Doing a little bit of cleanup.	mihad	7746d 23h	/pci/tags/rel_12/
96	Update!	mihad	7747d 00h	/pci/tags/rel_12/
95	Removed this file, because it was too large - long download time.	mihad	7747d 00h	/pci/tags/rel_12/
94	Changed one critical PCI bus signal logic.	mihad	7747d 00h	/pci/tags/rel_12/
93	Added a test application!	mihad	7747d 07h	/pci/tags/rel_12/
92	Update!	mihad	7747d 07h	/pci/tags/rel_12/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7782d 21h	/pci/tags/rel_12/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7782d 21h	/pci/tags/rel_12/
89	Burst 2 error fixed.	mihad	7818d 22h	/pci/tags/rel_12/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7824d 21h	/pci/tags/rel_12/
87	Updated acording to RTL changes.	mihad	7836d 18h	/pci/tags/rel_12/
86	Entered the option to disable no response counter in wb master.	mihad	7836d 18h	/pci/tags/rel_12/
85	Changed Vendor ID defines.	mihad	7836d 23h	/pci/tags/rel_12/
84	Changed vendor ID.	mihad	7840d 17h	/pci/tags/rel_12/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] - Rev 103

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