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[/] [pci/] [tags/] [rel_12/] - Rev 86

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Rev Log message Author Age Path
86 Entered the option to disable no response counter in wb master. mihad 7772d 11h /pci/tags/rel_12/
85 Changed Vendor ID defines. mihad 7772d 15h /pci/tags/rel_12/
84 Changed vendor ID. mihad 7776d 10h /pci/tags/rel_12/
83 Cleaned up the code. No functional changes. mihad 7801d 08h /pci/tags/rel_12/
81 Updated synchronization in top level fifo modules. mihad 7815d 05h /pci/tags/rel_12/
79 Updated. mihad 7818d 10h /pci/tags/rel_12/
78 Old files with wrong names removed. mihad 7818d 10h /pci/tags/rel_12/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7818d 10h /pci/tags/rel_12/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7821d 09h /pci/tags/rel_12/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7824d 10h /pci/tags/rel_12/
73 Bug fixes, testcases added. mihad 7824d 11h /pci/tags/rel_12/
72 *** empty log message *** mihad 7871d 14h /pci/tags/rel_12/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7879d 06h /pci/tags/rel_12/
69 Changed BIST signal names etc.. mihad 7916d 14h /pci/tags/rel_12/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7919d 23h /pci/tags/rel_12/
67 Changed BIST signals for RAMs. tadejm 7920d 04h /pci/tags/rel_12/
66 Changed empty status generation in pciw_fifo_control.v mihad 7923d 14h /pci/tags/rel_12/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7926d 12h /pci/tags/rel_12/
64 The testcase I just added in previous revision repaired mihad 7926d 15h /pci/tags/rel_12/
63 Added additional testcase and changed rst name in BIST to trst mihad 7926d 16h /pci/tags/rel_12/

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