URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 110

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7638d 06h	/pci/tags/rel_12/rtl/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7642d 04h	/pci/tags/rel_12/rtl/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7647d 02h	/pci/tags/rel_12/rtl/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7652d 12h	/pci/tags/rel_12/rtl/
94	Changed one critical PCI bus signal logic.	mihad	7699d 10h	/pci/tags/rel_12/rtl/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7777d 07h	/pci/tags/rel_12/rtl/
86	Entered the option to disable no response counter in wb master.	mihad	7789d 05h	/pci/tags/rel_12/rtl/
83	Cleaned up the code. No functional changes.	mihad	7818d 02h	/pci/tags/rel_12/rtl/
81	Updated synchronization in top level fifo modules.	mihad	7831d 22h	/pci/tags/rel_12/rtl/
79	Updated.	mihad	7835d 03h	/pci/tags/rel_12/rtl/
78	Old files with wrong names removed.	mihad	7835d 03h	/pci/tags/rel_12/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7835d 03h	/pci/tags/rel_12/rtl/
73	Bug fixes, testcases added.	mihad	7841d 04h	/pci/tags/rel_12/rtl/
72	* empty log message *	mihad	7888d 08h	/pci/tags/rel_12/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7896d 00h	/pci/tags/rel_12/rtl/
69	Changed BIST signal names etc..	mihad	7933d 07h	/pci/tags/rel_12/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7936d 17h	/pci/tags/rel_12/rtl/
67	Changed BIST signals for RAMs.	tadejm	7936d 21h	/pci/tags/rel_12/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7940d 08h	/pci/tags/rel_12/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7943d 06h	/pci/tags/rel_12/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 110

Filtering Options