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[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [bin/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5577d 03h /pci/tags/rel_12/sim/rtl_sim/bin/
129 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7495d 02h /pci/tags/rel_12/sim/rtl_sim/bin/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7541d 02h /pci/tags/rel_12/sim/rtl_sim/bin/
109 There was missing path to hdl.var file. tadejm 7617d 19h /pci/tags/rel_12/sim/rtl_sim/bin/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7622d 17h /pci/tags/rel_12/sim/rtl_sim/bin/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7810d 19h /pci/tags/rel_12/sim/rtl_sim/bin/
62 Added BIST signals for RAMs. mihad 7921d 18h /pci/tags/rel_12/sim/rtl_sim/bin/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7929d 18h /pci/tags/rel_12/sim/rtl_sim/bin/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7929d 19h /pci/tags/rel_12/sim/rtl_sim/bin/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7971d 19h /pci/tags/rel_12/sim/rtl_sim/bin/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7978d 00h /pci/tags/rel_12/sim/rtl_sim/bin/
27 Modified testbench and fixed some bugs mihad 8152d 18h /pci/tags/rel_12/sim/rtl_sim/bin/
26 Modified testbench and fixed some bugs mihad 8152d 19h /pci/tags/rel_12/sim/rtl_sim/bin/
16 Import of various scripts for simulation running mihad 8170d 22h /pci/tags/rel_12/sim/rtl_sim/bin/

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