URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [bin/] - Rev 109

Rev	Log message	Author	Age	Path
109	There was missing path to hdl.var file.	tadejm	7669d 00h	/pci/tags/rel_12/sim/rtl_sim/bin/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7673d 22h	/pci/tags/rel_12/sim/rtl_sim/bin/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7862d 00h	/pci/tags/rel_12/sim/rtl_sim/bin/
62	Added BIST signals for RAMs.	mihad	7972d 23h	/pci/tags/rel_12/sim/rtl_sim/bin/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7980d 23h	/pci/tags/rel_12/sim/rtl_sim/bin/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7981d 00h	/pci/tags/rel_12/sim/rtl_sim/bin/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8023d 00h	/pci/tags/rel_12/sim/rtl_sim/bin/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8029d 05h	/pci/tags/rel_12/sim/rtl_sim/bin/
27	Modified testbench and fixed some bugs	mihad	8203d 23h	/pci/tags/rel_12/sim/rtl_sim/bin/
26	Modified testbench and fixed some bugs	mihad	8204d 00h	/pci/tags/rel_12/sim/rtl_sim/bin/
16	Import of various scripts for simulation running	mihad	8222d 03h	/pci/tags/rel_12/sim/rtl_sim/bin/