OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5670d 19h /pci/tags/rel_12/sim/rtl_sim/run/
129 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7588d 18h /pci/tags/rel_12/sim/rtl_sim/run/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7634d 18h /pci/tags/rel_12/sim/rtl_sim/run/
118 Some minor changes due to changes in core. tadejm 7698d 07h /pci/tags/rel_12/sim/rtl_sim/run/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7716d 10h /pci/tags/rel_12/sim/rtl_sim/run/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7721d 19h /pci/tags/rel_12/sim/rtl_sim/run/
92 Update! mihad 7769d 01h /pci/tags/rel_12/sim/rtl_sim/run/
81 Updated synchronization in top level fifo modules. mihad 7901d 06h /pci/tags/rel_12/sim/rtl_sim/run/
73 Bug fixes, testcases added. mihad 7910d 12h /pci/tags/rel_12/sim/rtl_sim/run/
72 *** empty log message *** mihad 7957d 15h /pci/tags/rel_12/sim/rtl_sim/run/
63 Added additional testcase and changed rst name in BIST to trst mihad 8012d 18h /pci/tags/rel_12/sim/rtl_sim/run/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8023d 10h /pci/tags/rel_12/sim/rtl_sim/run/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8062d 19h /pci/tags/rel_12/sim/rtl_sim/run/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8071d 17h /pci/tags/rel_12/sim/rtl_sim/run/
42 Removed out of date files mihad 8083d 18h /pci/tags/rel_12/sim/rtl_sim/run/
26 Modified testbench and fixed some bugs mihad 8246d 11h /pci/tags/rel_12/sim/rtl_sim/run/
22 Added short description for simulation running mihad 8264d 12h /pci/tags/rel_12/sim/rtl_sim/run/
17 *** empty log message *** mihad 8264d 14h /pci/tags/rel_12/sim/rtl_sim/run/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.