URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [sim/] [rtl_sim/] [run/] - Rev 63

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	7942d 16h	/pci/tags/rel_12/sim/rtl_sim/run/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7953d 09h	/pci/tags/rel_12/sim/rtl_sim/run/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7992d 17h	/pci/tags/rel_12/sim/rtl_sim/run/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8001d 15h	/pci/tags/rel_12/sim/rtl_sim/run/
42	Removed out of date files	mihad	8013d 16h	/pci/tags/rel_12/sim/rtl_sim/run/
26	Modified testbench and fixed some bugs	mihad	8176d 10h	/pci/tags/rel_12/sim/rtl_sim/run/
22	Added short description for simulation running	mihad	8194d 10h	/pci/tags/rel_12/sim/rtl_sim/run/
17	* empty log message *	mihad	8194d 12h	/pci/tags/rel_12/sim/rtl_sim/run/