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[/] [pci/] [tags/] [rel_13/] - Rev 131

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Rev Log message Author Age Path
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.
mihad 7511d 23h /pci/tags/rel_13/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7517d 00h /pci/tags/rel_13/
128 Some warning cleanup. simons 7518d 02h /pci/tags/rel_13/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7525d 19h /pci/tags/rel_13/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7564d 02h /pci/tags/rel_13/
122 mbist signals updated according to newest convention markom 7571d 02h /pci/tags/rel_13/
119 Added support for WB B3. Some testcases were updated. tadejm 7627d 15h /pci/tags/rel_13/
118 Some minor changes due to changes in core. tadejm 7627d 15h /pci/tags/rel_13/
117 WB Master is now WISHBONE B3 compatible. tadejm 7627d 15h /pci/tags/rel_13/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7627d 15h /pci/tags/rel_13/
115 Added signals for WB Master B3. tadejm 7627d 15h /pci/tags/rel_13/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7634d 18h /pci/tags/rel_13/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7634d 22h /pci/tags/rel_13/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7636d 22h /pci/tags/rel_13/
109 There was missing path to hdl.var file. tadejm 7640d 19h /pci/tags/rel_13/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7640d 19h /pci/tags/rel_13/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7640d 19h /pci/tags/rel_13/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7645d 18h /pci/tags/rel_13/
105 Wrong pci_bridge32.v file included in the project! mihad 7651d 01h /pci/tags/rel_13/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7651d 03h /pci/tags/rel_13/

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