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[/] [pci/] [tags/] [rel_13/] [apps/] [crt/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5627d 10h /pci/tags/rel_13/apps/crt/
135 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7535d 07h /pci/tags/rel_13/apps/crt/
96 Update! mihad 7725d 08h /pci/tags/rel_13/apps/crt/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7761d 06h /pci/tags/rel_13/apps/crt/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7761d 06h /pci/tags/rel_13/apps/crt/
84 Changed vendor ID. mihad 7819d 01h /pci/tags/rel_13/apps/crt/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7861d 01h /pci/tags/rel_13/apps/crt/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7864d 01h /pci/tags/rel_13/apps/crt/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7867d 02h /pci/tags/rel_13/apps/crt/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7980d 02h /pci/tags/rel_13/apps/crt/
31 User defined constants used for Test Application tadej 8199d 22h /pci/tags/rel_13/apps/crt/
29 Xilinx synthesys log file tadej 8200d 09h /pci/tags/rel_13/apps/crt/
25 *** empty log message *** mihad 8221d 00h /pci/tags/rel_13/apps/crt/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8221d 03h /pci/tags/rel_13/apps/crt/
14 *** empty log message *** mihad 8221d 05h /pci/tags/rel_13/apps/crt/
2 New project directory structure mihad 8343d 03h /pci/tags/rel_13/apps/crt/

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