OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_13/] [bench/] - Rev 132

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
mihad 7494d 13h /pci/tags/rel_13/bench/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.
mihad 7498d 12h /pci/tags/rel_13/bench/
122 mbist signals updated according to newest convention markom 7557d 15h /pci/tags/rel_13/bench/
119 Added support for WB B3. Some testcases were updated. tadejm 7614d 03h /pci/tags/rel_13/bench/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7627d 08h /pci/tags/rel_13/bench/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7632d 06h /pci/tags/rel_13/bench/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7637d 16h /pci/tags/rel_13/bench/
92 Update! mihad 7684d 22h /pci/tags/rel_13/bench/
89 Burst 2 error fixed. mihad 7756d 12h /pci/tags/rel_13/bench/
87 Updated acording to RTL changes. mihad 7774d 08h /pci/tags/rel_13/bench/
81 Updated synchronization in top level fifo modules. mihad 7817d 02h /pci/tags/rel_13/bench/
73 Bug fixes, testcases added. mihad 7826d 08h /pci/tags/rel_13/bench/
69 Changed BIST signal names etc.. mihad 7918d 11h /pci/tags/rel_13/bench/
66 Changed empty status generation in pciw_fifo_control.v mihad 7925d 12h /pci/tags/rel_13/bench/
64 The testcase I just added in previous revision repaired mihad 7928d 12h /pci/tags/rel_13/bench/
63 Added additional testcase and changed rst name in BIST to trst mihad 7928d 14h /pci/tags/rel_13/bench/
62 Added BIST signals for RAMs. mihad 7931d 07h /pci/tags/rel_13/bench/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7944d 14h /pci/tags/rel_13/bench/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7978d 07h /pci/tags/rel_13/bench/
52 Oops, never before noticed that OC header is missing mihad 7978d 15h /pci/tags/rel_13/bench/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.