URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_13/] [rtl/] - Rev 113

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7661d 22h	/pci/tags/rel_13/rtl/
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7662d 03h	/pci/tags/rel_13/rtl/
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7664d 02h	/pci/tags/rel_13/rtl/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7667d 23h	/pci/tags/rel_13/rtl/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7672d 22h	/pci/tags/rel_13/rtl/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7678d 08h	/pci/tags/rel_13/rtl/
94	Changed one critical PCI bus signal logic.	mihad	7725d 06h	/pci/tags/rel_13/rtl/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7803d 03h	/pci/tags/rel_13/rtl/
86	Entered the option to disable no response counter in wb master.	mihad	7815d 01h	/pci/tags/rel_13/rtl/
83	Cleaned up the code. No functional changes.	mihad	7843d 22h	/pci/tags/rel_13/rtl/
81	Updated synchronization in top level fifo modules.	mihad	7857d 18h	/pci/tags/rel_13/rtl/
79	Updated.	mihad	7860d 23h	/pci/tags/rel_13/rtl/
78	Old files with wrong names removed.	mihad	7860d 23h	/pci/tags/rel_13/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7860d 23h	/pci/tags/rel_13/rtl/
73	Bug fixes, testcases added.	mihad	7867d 00h	/pci/tags/rel_13/rtl/
72	* empty log message *	mihad	7914d 04h	/pci/tags/rel_13/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7921d 19h	/pci/tags/rel_13/rtl/
69	Changed BIST signal names etc..	mihad	7959d 03h	/pci/tags/rel_13/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7962d 12h	/pci/tags/rel_13/rtl/
67	Changed BIST signals for RAMs.	tadejm	7962d 17h	/pci/tags/rel_13/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_13/] [rtl/] - Rev 113

Filtering Options