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[/] [pci/] [tags/] [rel_13/] [sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5586d 07h /pci/tags/rel_13/sim/
135 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7494d 05h /pci/tags/rel_13/sim/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7494d 05h /pci/tags/rel_13/sim/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7498d 03h /pci/tags/rel_13/sim/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7550d 06h /pci/tags/rel_13/sim/
118 Some minor changes due to changes in core. tadejm 7613d 19h /pci/tags/rel_13/sim/
109 There was missing path to hdl.var file. tadejm 7626d 23h /pci/tags/rel_13/sim/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7631d 22h /pci/tags/rel_13/sim/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7637d 07h /pci/tags/rel_13/sim/
95 Removed this file, because it was too large - long download time. mihad 7684d 06h /pci/tags/rel_13/sim/
92 Update! mihad 7684d 13h /pci/tags/rel_13/sim/
81 Updated synchronization in top level fifo modules. mihad 7816d 18h /pci/tags/rel_13/sim/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7819d 23h /pci/tags/rel_13/sim/
73 Bug fixes, testcases added. mihad 7826d 00h /pci/tags/rel_13/sim/
72 *** empty log message *** mihad 7873d 03h /pci/tags/rel_13/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7928d 06h /pci/tags/rel_13/sim/
62 Added BIST signals for RAMs. mihad 7930d 22h /pci/tags/rel_13/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7938d 22h /pci/tags/rel_13/sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7939d 00h /pci/tags/rel_13/sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7978d 07h /pci/tags/rel_13/sim/

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