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[/] [pci/] [tags/] [rel_13/] [sim/] [rtl_sim/] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5577d 02h	/pci/tags/rel_13/sim/rtl_sim/
135	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7484d 23h	/pci/tags/rel_13/sim/rtl_sim/
132	Compact PCI Hot Swap support added. New testcases added. Specification updated. Test application changed to support WB B3 cycles.	mihad	7484d 23h	/pci/tags/rel_13/sim/rtl_sim/
131	Moved top.v to bench directory. Removed unneeded meta_flop, modified files list files accordingly.	mihad	7488d 22h	/pci/tags/rel_13/sim/rtl_sim/
124	Added missing signals to 2 sensitivity lists. Everything works the same as before.	tadejm	7541d 00h	/pci/tags/rel_13/sim/rtl_sim/
118	Some minor changes due to changes in core.	tadejm	7604d 13h	/pci/tags/rel_13/sim/rtl_sim/
109	There was missing path to hdl.var file.	tadejm	7617d 17h	/pci/tags/rel_13/sim/rtl_sim/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7622d 16h	/pci/tags/rel_13/sim/rtl_sim/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7628d 02h	/pci/tags/rel_13/sim/rtl_sim/
95	Removed this file, because it was too large - long download time.	mihad	7675d 00h	/pci/tags/rel_13/sim/rtl_sim/
92	Update!	mihad	7675d 08h	/pci/tags/rel_13/sim/rtl_sim/
81	Updated synchronization in top level fifo modules.	mihad	7807d 12h	/pci/tags/rel_13/sim/rtl_sim/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7810d 17h	/pci/tags/rel_13/sim/rtl_sim/
73	Bug fixes, testcases added.	mihad	7816d 18h	/pci/tags/rel_13/sim/rtl_sim/
72	* empty log message *	mihad	7863d 22h	/pci/tags/rel_13/sim/rtl_sim/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7919d 00h	/pci/tags/rel_13/sim/rtl_sim/
62	Added BIST signals for RAMs.	mihad	7921d 17h	/pci/tags/rel_13/sim/rtl_sim/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7929d 17h	/pci/tags/rel_13/sim/rtl_sim/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7929d 18h	/pci/tags/rel_13/sim/rtl_sim/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7969d 01h	/pci/tags/rel_13/sim/rtl_sim/

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[/] [pci/] [tags/] [rel_13/] [sim/] [rtl_sim/] - Rev 154

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