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[/] [pci/] [tags/] [rel_13/] [sim/] [rtl_sim/] [bin/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5586d 16h /pci/tags/rel_13/sim/rtl_sim/bin/
135 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7494d 13h /pci/tags/rel_13/sim/rtl_sim/bin/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7494d 13h /pci/tags/rel_13/sim/rtl_sim/bin/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7498d 12h /pci/tags/rel_13/sim/rtl_sim/bin/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7550d 14h /pci/tags/rel_13/sim/rtl_sim/bin/
109 There was missing path to hdl.var file. tadejm 7627d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7632d 06h /pci/tags/rel_13/sim/rtl_sim/bin/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7820d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
62 Added BIST signals for RAMs. mihad 7931d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7939d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7939d 08h /pci/tags/rel_13/sim/rtl_sim/bin/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7981d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7987d 13h /pci/tags/rel_13/sim/rtl_sim/bin/
27 Modified testbench and fixed some bugs mihad 8162d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
26 Modified testbench and fixed some bugs mihad 8162d 07h /pci/tags/rel_13/sim/rtl_sim/bin/
16 Import of various scripts for simulation running mihad 8180d 10h /pci/tags/rel_13/sim/rtl_sim/bin/

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