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[/] [pci/] [tags/] [rel_13/] [sim/] [rtl_sim/] [run/] - Rev 135

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Rev Log message Author Age Path
135 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7536d 06h /pci/tags/rel_13/sim/rtl_sim/run/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7536d 06h /pci/tags/rel_13/sim/rtl_sim/run/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7592d 08h /pci/tags/rel_13/sim/rtl_sim/run/
118 Some minor changes due to changes in core. tadejm 7655d 21h /pci/tags/rel_13/sim/rtl_sim/run/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7674d 00h /pci/tags/rel_13/sim/rtl_sim/run/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7679d 09h /pci/tags/rel_13/sim/rtl_sim/run/
92 Update! mihad 7726d 15h /pci/tags/rel_13/sim/rtl_sim/run/
81 Updated synchronization in top level fifo modules. mihad 7858d 20h /pci/tags/rel_13/sim/rtl_sim/run/
73 Bug fixes, testcases added. mihad 7868d 02h /pci/tags/rel_13/sim/rtl_sim/run/
72 *** empty log message *** mihad 7915d 05h /pci/tags/rel_13/sim/rtl_sim/run/
63 Added additional testcase and changed rst name in BIST to trst mihad 7970d 07h /pci/tags/rel_13/sim/rtl_sim/run/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7981d 00h /pci/tags/rel_13/sim/rtl_sim/run/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8020d 09h /pci/tags/rel_13/sim/rtl_sim/run/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8029d 07h /pci/tags/rel_13/sim/rtl_sim/run/
42 Removed out of date files mihad 8041d 08h /pci/tags/rel_13/sim/rtl_sim/run/
26 Modified testbench and fixed some bugs mihad 8204d 01h /pci/tags/rel_13/sim/rtl_sim/run/
22 Added short description for simulation running mihad 8222d 02h /pci/tags/rel_13/sim/rtl_sim/run/
17 *** empty log message *** mihad 8222d 04h /pci/tags/rel_13/sim/rtl_sim/run/

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