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[/] [pci/] [tags/] [rel_2/] [rtl/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5568d 07h /pci/tags/rel_2/rtl/verilog/
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7900d 02h /pci/tags/rel_2/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7900d 02h /pci/tags/rel_2/rtl/verilog/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7903d 12h /pci/tags/rel_2/rtl/verilog/
67 Changed BIST signals for RAMs. tadejm 7903d 16h /pci/tags/rel_2/rtl/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7907d 03h /pci/tags/rel_2/rtl/verilog/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7910d 01h /pci/tags/rel_2/rtl/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7910d 05h /pci/tags/rel_2/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7912d 22h /pci/tags/rel_2/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7920d 22h /pci/tags/rel_2/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7920d 23h /pci/tags/rel_2/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7925d 23h /pci/tags/rel_2/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7926d 05h /pci/tags/rel_2/rtl/verilog/
56 Number of state bits define was removed mihad 7926d 20h /pci/tags/rel_2/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7926d 21h /pci/tags/rel_2/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7960d 02h /pci/tags/rel_2/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7960d 06h /pci/tags/rel_2/rtl/verilog/
50 Got rid of undef directives mihad 7962d 22h /pci/tags/rel_2/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7962d 22h /pci/tags/rel_2/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7962d 22h /pci/tags/rel_2/rtl/verilog/

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