URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] - Rev 27

Rev	Log message	Author	Age	Path
27	Modified testbench and fixed some bugs	mihad	8165d 09h	/pci/tags/rel_3/
26	Modified testbench and fixed some bugs	mihad	8165d 10h	/pci/tags/rel_3/
25	* empty log message *	mihad	8183d 09h	/pci/tags/rel_3/
24	* empty log message *	mihad	8183d 09h	/pci/tags/rel_3/
23	* empty log message *	mihad	8183d 11h	/pci/tags/rel_3/
22	Added short description for simulation running	mihad	8183d 11h	/pci/tags/rel_3/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8183d 11h	/pci/tags/rel_3/
20	* empty log message *	mihad	8183d 11h	/pci/tags/rel_3/
19	* empty log message *	mihad	8183d 11h	/pci/tags/rel_3/
18	* empty log message *	mihad	8183d 12h	/pci/tags/rel_3/
17	* empty log message *	mihad	8183d 13h	/pci/tags/rel_3/
16	Import of various scripts for simulation running	mihad	8183d 13h	/pci/tags/rel_3/
15	Initial testbench import. Still under development	mihad	8183d 13h	/pci/tags/rel_3/
14	* empty log message *	mihad	8183d 13h	/pci/tags/rel_3/
13	Added separate software directory to the project	mihad	8183d 13h	/pci/tags/rel_3/
12	PCI IP Core Introduction	mihad	8185d 09h	/pci/tags/rel_3/
11	Initial design document release	mihad	8185d 09h	/pci/tags/rel_3/
10	Updated descriptions, functional changes, added software obligations chapter	mihad	8185d 09h	/pci/tags/rel_3/
9	Update the Configuration Space and REGISTERS description	mihad	8285d 17h	/pci/tags/rel_3/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8302d 18h	/pci/tags/rel_3/