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[/] [pci/] [tags/] [rel_3/] [rtl/] - Rev 63

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Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7929d 14h /pci/tags/rel_3/rtl/
62 Added BIST signals for RAMs. mihad 7932d 07h /pci/tags/rel_3/rtl/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7940d 07h /pci/tags/rel_3/rtl/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7940d 08h /pci/tags/rel_3/rtl/
58 Removed all logic from asynchronous reset network mihad 7945d 08h /pci/tags/rel_3/rtl/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7945d 14h /pci/tags/rel_3/rtl/
56 Number of state bits define was removed mihad 7946d 05h /pci/tags/rel_3/rtl/
55 Changed state machine encoding to true one-hot mihad 7946d 06h /pci/tags/rel_3/rtl/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7979d 11h /pci/tags/rel_3/rtl/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7979d 15h /pci/tags/rel_3/rtl/
50 Got rid of undef directives mihad 7982d 07h /pci/tags/rel_3/rtl/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7982d 07h /pci/tags/rel_3/rtl/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7982d 08h /pci/tags/rel_3/rtl/
47 Known issues repaired mihad 7982d 13h /pci/tags/rel_3/rtl/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7987d 08h /pci/tags/rel_3/rtl/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7988d 13h /pci/tags/rel_3/rtl/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8133d 17h /pci/tags/rel_3/rtl/
33 Added some testcases, removed un-needed fifo signals mihad 8149d 12h /pci/tags/rel_3/rtl/
32 Added include statement that was missing and causing errors mihad 8157d 09h /pci/tags/rel_3/rtl/
26 Modified testbench and fixed some bugs mihad 8163d 08h /pci/tags/rel_3/rtl/

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