OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7803d 15h /pci/tags/rel_3/rtl/
73 Bug fixes, testcases added. mihad 7803d 15h /pci/tags/rel_3/rtl/
72 *** empty log message *** mihad 7850d 18h /pci/tags/rel_3/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7858d 10h /pci/tags/rel_3/rtl/
69 Changed BIST signal names etc.. mihad 7895d 18h /pci/tags/rel_3/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7899d 03h /pci/tags/rel_3/rtl/
67 Changed BIST signals for RAMs. tadejm 7899d 08h /pci/tags/rel_3/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7902d 18h /pci/tags/rel_3/rtl/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7905d 16h /pci/tags/rel_3/rtl/
63 Added additional testcase and changed rst name in BIST to trst mihad 7905d 21h /pci/tags/rel_3/rtl/
62 Added BIST signals for RAMs. mihad 7908d 13h /pci/tags/rel_3/rtl/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7916d 13h /pci/tags/rel_3/rtl/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7916d 15h /pci/tags/rel_3/rtl/
58 Removed all logic from asynchronous reset network mihad 7921d 15h /pci/tags/rel_3/rtl/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7921d 21h /pci/tags/rel_3/rtl/
56 Number of state bits define was removed mihad 7922d 12h /pci/tags/rel_3/rtl/
55 Changed state machine encoding to true one-hot mihad 7922d 12h /pci/tags/rel_3/rtl/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7955d 17h /pci/tags/rel_3/rtl/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7955d 22h /pci/tags/rel_3/rtl/
50 Got rid of undef directives mihad 7958d 14h /pci/tags/rel_3/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.