URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 45

Rev	Log message	Author	Age	Path
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7991d 01h	/pci/tags/rel_3/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8136d 04h	/pci/tags/rel_3/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8152d 00h	/pci/tags/rel_3/rtl/verilog/
32	Added include statement that was missing and causing errors	mihad	8159d 21h	/pci/tags/rel_3/rtl/verilog/
26	Modified testbench and fixed some bugs	mihad	8165d 19h	/pci/tags/rel_3/rtl/verilog/
23	* empty log message *	mihad	8183d 20h	/pci/tags/rel_3/rtl/verilog/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8183d 20h	/pci/tags/rel_3/rtl/verilog/
19	* empty log message *	mihad	8183d 21h	/pci/tags/rel_3/rtl/verilog/
18	* empty log message *	mihad	8183d 21h	/pci/tags/rel_3/rtl/verilog/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8303d 04h	/pci/tags/rel_3/rtl/verilog/
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8303d 04h	/pci/tags/rel_3/rtl/verilog/
2	New project directory structure	mihad	8305d 20h	/pci/tags/rel_3/rtl/verilog/