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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 74

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Rev	Log message	Author	Age	Path
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7820d 08h	/pci/tags/rel_3/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7820d 08h	/pci/tags/rel_3/rtl/verilog/
72	* empty log message *	mihad	7867d 12h	/pci/tags/rel_3/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7875d 04h	/pci/tags/rel_3/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7912d 11h	/pci/tags/rel_3/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7915d 21h	/pci/tags/rel_3/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7916d 01h	/pci/tags/rel_3/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7919d 12h	/pci/tags/rel_3/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7922d 10h	/pci/tags/rel_3/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7922d 14h	/pci/tags/rel_3/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7925d 07h	/pci/tags/rel_3/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7933d 07h	/pci/tags/rel_3/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7933d 08h	/pci/tags/rel_3/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7938d 08h	/pci/tags/rel_3/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7938d 14h	/pci/tags/rel_3/rtl/verilog/
56	Number of state bits define was removed	mihad	7939d 05h	/pci/tags/rel_3/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7939d 06h	/pci/tags/rel_3/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7972d 11h	/pci/tags/rel_3/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7972d 15h	/pci/tags/rel_3/rtl/verilog/
50	Got rid of undef directives	mihad	7975d 07h	/pci/tags/rel_3/rtl/verilog/

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 74

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