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[/] [pci/] [tags/] [rel_4/] - Rev 67

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Rev Log message Author Age Path
67 Changed BIST signals for RAMs. tadejm 8006d 19h /pci/tags/rel_4/
66 Changed empty status generation in pciw_fifo_control.v mihad 8010d 05h /pci/tags/rel_4/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8013d 03h /pci/tags/rel_4/
64 The testcase I just added in previous revision repaired mihad 8013d 06h /pci/tags/rel_4/
63 Added additional testcase and changed rst name in BIST to trst mihad 8013d 07h /pci/tags/rel_4/
62 Added BIST signals for RAMs. mihad 8016d 00h /pci/tags/rel_4/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8024d 00h /pci/tags/rel_4/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8024d 02h /pci/tags/rel_4/
58 Removed all logic from asynchronous reset network mihad 8029d 02h /pci/tags/rel_4/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8029d 08h /pci/tags/rel_4/
56 Number of state bits define was removed mihad 8029d 22h /pci/tags/rel_4/
55 Changed state machine encoding to true one-hot mihad 8029d 23h /pci/tags/rel_4/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8063d 01h /pci/tags/rel_4/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8063d 04h /pci/tags/rel_4/
52 Oops, never before noticed that OC header is missing mihad 8063d 08h /pci/tags/rel_4/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8063d 08h /pci/tags/rel_4/
50 Got rid of undef directives mihad 8066d 01h /pci/tags/rel_4/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8066d 01h /pci/tags/rel_4/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8066d 01h /pci/tags/rel_4/
47 Known issues repaired mihad 8066d 07h /pci/tags/rel_4/

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