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[/] [pci/] [tags/] [rel_4/] - Rev 76

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Rev	Log message	Author	Age	Path
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7904d 11h	/pci/tags/rel_4/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7907d 12h	/pci/tags/rel_4/
73	Bug fixes, testcases added.	mihad	7907d 13h	/pci/tags/rel_4/
72	* empty log message *	mihad	7954d 16h	/pci/tags/rel_4/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7962d 08h	/pci/tags/rel_4/
69	Changed BIST signal names etc..	mihad	7999d 16h	/pci/tags/rel_4/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8003d 01h	/pci/tags/rel_4/
67	Changed BIST signals for RAMs.	tadejm	8003d 06h	/pci/tags/rel_4/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8006d 16h	/pci/tags/rel_4/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8009d 14h	/pci/tags/rel_4/
64	The testcase I just added in previous revision repaired	mihad	8009d 17h	/pci/tags/rel_4/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8009d 18h	/pci/tags/rel_4/
62	Added BIST signals for RAMs.	mihad	8012d 11h	/pci/tags/rel_4/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8020d 11h	/pci/tags/rel_4/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8020d 13h	/pci/tags/rel_4/
58	Removed all logic from asynchronous reset network	mihad	8025d 13h	/pci/tags/rel_4/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8025d 19h	/pci/tags/rel_4/
56	Number of state bits define was removed	mihad	8026d 09h	/pci/tags/rel_4/
55	Changed state machine encoding to true one-hot	mihad	8026d 10h	/pci/tags/rel_4/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8059d 12h	/pci/tags/rel_4/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_4/] - Rev 76

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