URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] - Rev 42

Rev	Log message	Author	Age	Path
42	Removed out of date files	mihad	8008d 00h	/pci/tags/rel_5/
40	From these Wrod files PDF were created - added future improvements	tadej	8086d 15h	/pci/tags/rel_5/
39	File not needed	tadej	8086d 15h	/pci/tags/rel_5/
38	This file is not needed	tadej	8086d 18h	/pci/tags/rel_5/
37	These files are not needed any more	tadej	8086d 18h	/pci/tags/rel_5/
36	* empty log message *	tadej	8086d 19h	/pci/tags/rel_5/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8141d 02h	/pci/tags/rel_5/
34	Added missing include statements	mihad	8156d 01h	/pci/tags/rel_5/
33	Added some testcases, removed un-needed fifo signals	mihad	8156d 22h	/pci/tags/rel_5/
32	Added include statement that was missing and causing errors	mihad	8164d 19h	/pci/tags/rel_5/
31	User defined constants used for Test Application	tadej	8167d 14h	/pci/tags/rel_5/
30	Example of PCI testbench log file	mihad	8167d 22h	/pci/tags/rel_5/
29	Xilinx synthesys log file	tadej	8168d 01h	/pci/tags/rel_5/
28	pci/doc/pci_databook.pdf	tadej	8168d 19h	/pci/tags/rel_5/
27	Modified testbench and fixed some bugs	mihad	8170d 17h	/pci/tags/rel_5/
26	Modified testbench and fixed some bugs	mihad	8170d 17h	/pci/tags/rel_5/
25	* empty log message *	mihad	8188d 16h	/pci/tags/rel_5/
24	* empty log message *	mihad	8188d 16h	/pci/tags/rel_5/
23	* empty log message *	mihad	8188d 18h	/pci/tags/rel_5/
22	Added short description for simulation running	mihad	8188d 18h	/pci/tags/rel_5/