URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [tags/] [rel_5/] - Rev 50

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Rev	Log message	Author	Age	Path
50	Got rid of undef directives	mihad	7981d 06h	/pci/tags/rel_5/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7981d 06h	/pci/tags/rel_5/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7981d 06h	/pci/tags/rel_5/
47	Known issues repaired	mihad	7981d 12h	/pci/tags/rel_5/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7986d 06h	/pci/tags/rel_5/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7987d 12h	/pci/tags/rel_5/
44	Added for testing of Configuration Cycles Type 1	mihad	7987d 12h	/pci/tags/rel_5/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7987d 12h	/pci/tags/rel_5/
42	Removed out of date files	mihad	7999d 13h	/pci/tags/rel_5/
40	From these Wrod files PDF were created - added future improvements	tadej	8078d 04h	/pci/tags/rel_5/
39	File not needed	tadej	8078d 04h	/pci/tags/rel_5/
38	This file is not needed	tadej	8078d 07h	/pci/tags/rel_5/
37	These files are not needed any more	tadej	8078d 07h	/pci/tags/rel_5/
36	* empty log message *	tadej	8078d 08h	/pci/tags/rel_5/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8132d 15h	/pci/tags/rel_5/
34	Added missing include statements	mihad	8147d 14h	/pci/tags/rel_5/
33	Added some testcases, removed un-needed fifo signals	mihad	8148d 11h	/pci/tags/rel_5/
32	Added include statement that was missing and causing errors	mihad	8156d 08h	/pci/tags/rel_5/
31	User defined constants used for Test Application	tadej	8159d 03h	/pci/tags/rel_5/
30	Example of PCI testbench log file	mihad	8159d 11h	/pci/tags/rel_5/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] - Rev 50

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