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[/] [pci/] [tags/] [rel_5/] - Rev 73

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Rev	Log message	Author	Age	Path
73	Bug fixes, testcases added.	mihad	7826d 08h	/pci/tags/rel_5/
72	* empty log message *	mihad	7873d 11h	/pci/tags/rel_5/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7881d 03h	/pci/tags/rel_5/
69	Changed BIST signal names etc..	mihad	7918d 11h	/pci/tags/rel_5/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7921d 20h	/pci/tags/rel_5/
67	Changed BIST signals for RAMs.	tadejm	7922d 01h	/pci/tags/rel_5/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 11h	/pci/tags/rel_5/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 09h	/pci/tags/rel_5/
64	The testcase I just added in previous revision repaired	mihad	7928d 12h	/pci/tags/rel_5/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 14h	/pci/tags/rel_5/
62	Added BIST signals for RAMs.	mihad	7931d 06h	/pci/tags/rel_5/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 06h	/pci/tags/rel_5/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 08h	/pci/tags/rel_5/
58	Removed all logic from asynchronous reset network	mihad	7944d 08h	/pci/tags/rel_5/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7944d 14h	/pci/tags/rel_5/
56	Number of state bits define was removed	mihad	7945d 05h	/pci/tags/rel_5/
55	Changed state machine encoding to true one-hot	mihad	7945d 05h	/pci/tags/rel_5/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7978d 07h	/pci/tags/rel_5/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7978d 10h	/pci/tags/rel_5/
52	Oops, never before noticed that OC header is missing	mihad	7978d 14h	/pci/tags/rel_5/

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[/] [pci/] [tags/] [rel_5/] - Rev 73

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