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[/] [pci/] [tags/] [rel_5/] - Rev 82

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Rev	Log message	Author	Age	Path
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7825d 04h	/pci/tags/rel_5/
81	Updated synchronization in top level fifo modules.	mihad	7825d 04h	/pci/tags/rel_5/
79	Updated.	mihad	7828d 09h	/pci/tags/rel_5/
78	Old files with wrong names removed.	mihad	7828d 09h	/pci/tags/rel_5/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7828d 09h	/pci/tags/rel_5/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7831d 09h	/pci/tags/rel_5/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7834d 10h	/pci/tags/rel_5/
73	Bug fixes, testcases added.	mihad	7834d 10h	/pci/tags/rel_5/
72	* empty log message *	mihad	7881d 14h	/pci/tags/rel_5/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7889d 05h	/pci/tags/rel_5/
69	Changed BIST signal names etc..	mihad	7926d 13h	/pci/tags/rel_5/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7929d 22h	/pci/tags/rel_5/
67	Changed BIST signals for RAMs.	tadejm	7930d 03h	/pci/tags/rel_5/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7933d 14h	/pci/tags/rel_5/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7936d 12h	/pci/tags/rel_5/
64	The testcase I just added in previous revision repaired	mihad	7936d 14h	/pci/tags/rel_5/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7936d 16h	/pci/tags/rel_5/
62	Added BIST signals for RAMs.	mihad	7939d 09h	/pci/tags/rel_5/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7947d 09h	/pci/tags/rel_5/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7947d 10h	/pci/tags/rel_5/

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[/] [pci/] [tags/] [rel_5/] - Rev 82

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