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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5567d 12h /pci/tags/rel_5/bench/verilog/
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7797d 22h /pci/tags/rel_5/bench/verilog/
81 Updated synchronization in top level fifo modules. mihad 7797d 22h /pci/tags/rel_5/bench/verilog/
73 Bug fixes, testcases added. mihad 7807d 04h /pci/tags/rel_5/bench/verilog/
69 Changed BIST signal names etc.. mihad 7899d 07h /pci/tags/rel_5/bench/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7906d 08h /pci/tags/rel_5/bench/verilog/
64 The testcase I just added in previous revision repaired mihad 7909d 08h /pci/tags/rel_5/bench/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7909d 10h /pci/tags/rel_5/bench/verilog/
62 Added BIST signals for RAMs. mihad 7912d 03h /pci/tags/rel_5/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7925d 10h /pci/tags/rel_5/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7959d 03h /pci/tags/rel_5/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7959d 11h /pci/tags/rel_5/bench/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7959d 11h /pci/tags/rel_5/bench/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7968d 09h /pci/tags/rel_5/bench/verilog/
44 Added for testing of Configuration Cycles Type 1 mihad 7968d 09h /pci/tags/rel_5/bench/verilog/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7968d 09h /pci/tags/rel_5/bench/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8113d 12h /pci/tags/rel_5/bench/verilog/
34 Added missing include statements mihad 8128d 11h /pci/tags/rel_5/bench/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8129d 08h /pci/tags/rel_5/bench/verilog/
26 Modified testbench and fixed some bugs mihad 8143d 03h /pci/tags/rel_5/bench/verilog/

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