URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] - Rev 52

Rev	Log message	Author	Age	Path
52	Oops, never before noticed that OC header is missing	mihad	8020d 05h	/pci/tags/rel_5/bench/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8020d 05h	/pci/tags/rel_5/bench/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8029d 03h	/pci/tags/rel_5/bench/verilog/
44	Added for testing of Configuration Cycles Type 1	mihad	8029d 04h	/pci/tags/rel_5/bench/verilog/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8029d 04h	/pci/tags/rel_5/bench/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8174d 07h	/pci/tags/rel_5/bench/verilog/
34	Added missing include statements	mihad	8189d 05h	/pci/tags/rel_5/bench/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8190d 03h	/pci/tags/rel_5/bench/verilog/
26	Modified testbench and fixed some bugs	mihad	8203d 22h	/pci/tags/rel_5/bench/verilog/
19	* empty log message *	mihad	8221d 23h	/pci/tags/rel_5/bench/verilog/
15	Initial testbench import. Still under development	mihad	8222d 01h	/pci/tags/rel_5/bench/verilog/
3	New project directory structure	mihad	8343d 23h	/pci/tags/rel_5/bench/verilog/