OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] - Rev 63

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7936d 18h /pci/tags/rel_5/bench/verilog/
62 Added BIST signals for RAMs. mihad 7939d 11h /pci/tags/rel_5/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7952d 18h /pci/tags/rel_5/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7986d 11h /pci/tags/rel_5/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7986d 19h /pci/tags/rel_5/bench/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7986d 19h /pci/tags/rel_5/bench/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7995d 17h /pci/tags/rel_5/bench/verilog/
44 Added for testing of Configuration Cycles Type 1 mihad 7995d 17h /pci/tags/rel_5/bench/verilog/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7995d 17h /pci/tags/rel_5/bench/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8140d 20h /pci/tags/rel_5/bench/verilog/
34 Added missing include statements mihad 8155d 19h /pci/tags/rel_5/bench/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8156d 16h /pci/tags/rel_5/bench/verilog/
26 Modified testbench and fixed some bugs mihad 8170d 11h /pci/tags/rel_5/bench/verilog/
19 *** empty log message *** mihad 8188d 13h /pci/tags/rel_5/bench/verilog/
15 Initial testbench import. Still under development mihad 8188d 14h /pci/tags/rel_5/bench/verilog/
3 New project directory structure mihad 8310d 12h /pci/tags/rel_5/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.