URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 62

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
62	Added BIST signals for RAMs.	mihad	7930d 12h	/pci/tags/rel_5/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7938d 12h	/pci/tags/rel_5/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7938d 13h	/pci/tags/rel_5/rtl/
58	Removed all logic from asynchronous reset network	mihad	7943d 13h	/pci/tags/rel_5/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7943d 19h	/pci/tags/rel_5/rtl/
56	Number of state bits define was removed	mihad	7944d 10h	/pci/tags/rel_5/rtl/
55	Changed state machine encoding to true one-hot	mihad	7944d 11h	/pci/tags/rel_5/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7977d 16h	/pci/tags/rel_5/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7977d 20h	/pci/tags/rel_5/rtl/
50	Got rid of undef directives	mihad	7980d 12h	/pci/tags/rel_5/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7980d 12h	/pci/tags/rel_5/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7980d 12h	/pci/tags/rel_5/rtl/
47	Known issues repaired	mihad	7980d 18h	/pci/tags/rel_5/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7985d 12h	/pci/tags/rel_5/rtl/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7986d 18h	/pci/tags/rel_5/rtl/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8131d 21h	/pci/tags/rel_5/rtl/
33	Added some testcases, removed un-needed fifo signals	mihad	8147d 17h	/pci/tags/rel_5/rtl/
32	Added include statement that was missing and causing errors	mihad	8155d 14h	/pci/tags/rel_5/rtl/
26	Modified testbench and fixed some bugs	mihad	8161d 12h	/pci/tags/rel_5/rtl/
23	* empty log message *	mihad	8179d 13h	/pci/tags/rel_5/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 62

Filtering Options