OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [sim/] - Rev 77

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7819d 03h /pci/tags/rel_5/sim/
73 Bug fixes, testcases added. mihad 7825d 04h /pci/tags/rel_5/sim/
72 *** empty log message *** mihad 7872d 08h /pci/tags/rel_5/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7927d 10h /pci/tags/rel_5/sim/
62 Added BIST signals for RAMs. mihad 7930d 03h /pci/tags/rel_5/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7938d 03h /pci/tags/rel_5/sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7938d 04h /pci/tags/rel_5/sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7977d 11h /pci/tags/rel_5/sim/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7980d 03h /pci/tags/rel_5/sim/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7986d 09h /pci/tags/rel_5/sim/
42 Removed out of date files mihad 7998d 10h /pci/tags/rel_5/sim/
30 Example of PCI testbench log file mihad 8158d 08h /pci/tags/rel_5/sim/
27 Modified testbench and fixed some bugs mihad 8161d 03h /pci/tags/rel_5/sim/
26 Modified testbench and fixed some bugs mihad 8161d 04h /pci/tags/rel_5/sim/
22 Added short description for simulation running mihad 8179d 04h /pci/tags/rel_5/sim/
20 *** empty log message *** mihad 8179d 05h /pci/tags/rel_5/sim/
17 *** empty log message *** mihad 8179d 06h /pci/tags/rel_5/sim/
16 Import of various scripts for simulation running mihad 8179d 06h /pci/tags/rel_5/sim/
3 New project directory structure mihad 8301d 04h /pci/tags/rel_5/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.